This invention relates to communication data switching and more particularly relates to such switching of data organized in frames which accommodate groups of data of different sizes.
In the field of telecommunications, there are a number of standard frame formats which are built from successive combinations of fundamental 64 KBit/sec. channels. Each channel is represented as 8 bits transmitted every 125 microseconds (uS) (also referred to as a DS0 channel or an E0 channel). One such format is SONET (Synchronous Optical Network) which creates 125 uS frames containing Virtual Tributaries (VTs). The size of the VTs depends on the underlying payload being transported within a SONET frame. VT sizes include VT1.5, VT2, VT3 and VT6.
Of particular interest are the VT1.5 and VT2. The VT1.5 contains a total of 27 bytes of 8 bits per 125 uS frame and was sized to accommodate a DS1 payload. A DS1 is a standard format comprised of 193 bits per 125 uS frame—192 bits representing twenty-four DS0s and 1 overhead bit. Twenty-eight VT1.5s can be placed within a SONET STS-1 Synchronous Payload Envelope (SPE), the payload part of a SONET STS-1 transport frame. The VT2 contains a total of 36 bytes of 8 bits per 125 uS frame and was sized to accommodate an E1 payload. An E1 has 256 bits per 125 uS frame—240 bits representing thirty E0s and 16 overhead bits. Twenty-one VT2s can fit in an SONET STS-1 SPE. The STS-1 SPE is segmented into 7 VT Groups. Each VT Group can contain 4 VT1.5s or 3 VT2s.
Manipulation of traffic contained within a SONET STS-n SPE requires the ability to interchange VTs from one SONET stream to another. Switch fabrics exist which are optimized based on the level of hierarchy they need to operate. To be a totally non-blocking VT-level switch, it must be true that any incoming VT position in a SONET frame can be mapped to any same-sized free VT position in an outgoing SONET frame. This requires both time and space manipulation by the switch fabric. Typical switch network architectures to perform these functions are known to be realized by cascading time and space switch elements. One known example of this type of architecture is the T-S-T architecture, where the signals pass through a total of three network stages, the first and last of which are time switched, and the middle of which is space switched. Furthermore, a different type of switch architecture using a three stage space switching network could be used to give a T-S-S-S-T type configuration.
FIG. 1 illustrates how the payload of an STS-1 can be reconfigured for optimal switching of VT1.5s or VT2s. The STS-1 SPE overhead and fixed stuff columns are discarded as they are not needed for VT-level mappings and cross-connection. These mappings typically assume that the entire payload is composed of VT sizes that are either all multiples of VT1.5 or all multiples of VT2. In both configurations, the number of columns is minimized to provide the desired level of switching with minimal memory and time switch delay.
Time switching involves re-ordering the time sequence (or VT position) of the VTs within a single SONET frame. This typically is realized by buffering the input stream such that as each output byte is required, a stable sample of the previous byte from any input timeslot (or VT position) is guaranteed to be available. In the case of a VT1.5 time switch for instance, 28 bytes of storage are required. For a VT2 time switch, 21 bytes of storage are required. A significant delay in the data path results from this input buffering with the delay being a function of the resolution required of the switch fabric (the lower the resolution, the longer the delay). Lower resolution also increases memory size and power dissipation.
Space switching is equivalent to a crossbar function where a given output's content can be based on one of several inputs. To achieve VT level switching, the selection of the input must be dynamic such that each VT timeslot in the SONET frame can have a unique mapping. Essentially no data delay is incurred in space switching. Resolution level in a space switching element does impact memory size and power dissipation, though not to the same degree experienced by the time switch stage.
For both time and space switching, the resolution of the fabric is typically consistent, and generally is set up to handle either VT1.5 or VT2 signals. However, the STS-1 frames could contain some VT Groups carrying VT1.5s and some containing VT2s. This presents a challenge, because systems optimized for manipulating VT1.5s cannot handle VT2s efficiently. Such a system would either need to have the VT2 distributed over 2 VT1.5s, which would then be mapped together through the fabric (resulting in a 33% loss of bandwidth efficiency as shown in FIG. 2), or it would be necessary to switch VT Groups with VT2s at the VT Group level (with a loss in routing flexibility, as all 3 VT2s would need to stay in that VT Group as it passes through the fabric). The reverse is also true. A system optimized for VT2 switching will not be able to accommodate VT1.5 manipulation without first mapping the VT1.5s into VT2s (resulting in a 25% bandwidth efficiency loss as shown in FIG. 3) or again resorting to switching the VT Group containing VT1.5s intact through the fabric.
A common method of handling “mixed traffic” composed of VT1.5s and VT2s is to employ a DS0/E0 level switch. The fabric can manipulate VT1.5s and VT2s without any lost bandwidth efficiency. The disadvantage lies in the large increase in data delay (˜125 uS per time switch stage) and memory for storing connections and data. This is due to the need to store a full 125 uS frame of data in the time switch as opposed to only one byte per VT1.5 or VT2. These issues either eliminate this approach (data delay beyond network requirements) or reduce density (large memories restrict the capacity of individual switch elements).
Other fabrics have been proposed which operate on a 100 column basis, capable of manipulating VT traffic of any size by concatenating ˜0.5 Mbps payload containers to form the various VT sizes. For example, see U.S. Pat. No. 5,579,310 (Heiles et al., issued Nov. 26, 1996). This frame structure, however, cannot directly support multi-rate timeslot interchange capability due to the fact that 100 is not evenly divisible by both 3 and 4 (i.e., has a least common multiple of 12). For this reason, all timeslot interchange stages in this approach have to buffer all 100 columns (timeslots), thereby causing a maximum throughput delay, regardless of whether only one type of VT traffic is being switched or not.
Another approach is described in U.S. Pat. No. 5,144,297 (Ohara, issued Sep. 1, 1992) which describes the processing of data in 36 byte increments (FIGS. 5-10). Such an approach is inefficient because four STS-1 frames need to be stored before all 36 bytes of the processing increment are available. Furthermore, since overhead is added to each of the 36 byte increments, the ratio of overhead to usable payload data is less efficient, and the processing required to manipulate the overhead is significantly more involved than structures proposed herein, where the overhead is shared among several VTs equivalents interleaved to form an STS-1 SPE equivalent structure.